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Data Sheet, Rev. 1.10, Mar. 2006
HYS72T64000HR-[3.7/5]-B HYS72T1280x0HR-[3.7/5]-B HYS72T256220HR-[3.7/5]-B
240-Pin Registered DDR2 SDRAM Modules
RDIMM SDRAM DDR2 SDRAM RoHS Compliant
Memory Products
Edition 2006-03 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2006. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
HYS72T64000HR-[3.7/5]-B, HYS72T1280x0HR-[3.7/5]-B, HYS72T256220HR-[3.7/5]-B, Revision History: 2006-03, 1.10 Page 5 8 23,25,35, 36 45 Subjects (major changes since last revision) removed product types for DDR800,DRR667 these are to be found in a separate data sheet removed DDR800, DDR667 raw card figures removed DDR800, DDR667 tables removed DDR800, DDR667 package outlines Previous Revision: 2005-07,1.00
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Template: mp_a4_s_rev321 / 3 / 2005-10-05
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Table of Contents 1 1.1 1.2 2 2.1 2.2 3 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.4 3.4.1 3.4.2 4 5 6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration and Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDD Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On Die Termination (ODT) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 21 21 23 23 25 29 30 34 35
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Product Type Nomenclature (DDR2 DRAMs and DIMMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Data Sheet
4
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
240-Pin Registered DDR2 SDRAM Modules RDIMM SDRAM
HYS72T64000HR-[3.7/5]-B HYS72T1280x0HR-[3.7/5]-B HYS72T256220HR-[3.7/5]-B
1
Overview
This chapter gives an overview of the 1.8 V 240-Pin Registered DDR2 SDRAM Modules product family and describes its main characteristics.
1.1
*
Features
* * * * * * * * * Programmable partial array refresh via EMRS2 settings DCC enabling via EMRS2 setting All inputs and outputs SSTL_18 compatible Off-Chip Driver Impedance Adjustment (OCD) and On-Die Termination (ODT) Serial Presence Detect with E2PROM RDIMM Dimensions (nominal): 30,00 mm high, 133.35 mm wide Based on standard reference card layouts Raw Card "A", "B", "C", "J" All speed grades faster than DDR400 comply with DDR400 timing specifications. RoHS compliant products1)
*
*
* * * *
240-Pin PC2-6400, PC2-5300PC2-4200 and PC2-3200 DDR2 SDRAM memory modules for PC, Workstation and Server main memory applications. One rank 64M x72, 128M x72, and two ranks 128M x72, 256M x72 module organization, and 512M x8, 512M x4 chip organization Standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V ( 0.1 V) power supply Built with 512 Mbit DDR2 SDRAMs in P-TFBGA-60 chipsize packages. Programmable CAS Latencies (3, 4, 5, 6), Burst Length (4 & 8) and Burst Type Auto Refresh (CBR) and Self Refresh Programmable self refresh rate via EMRS2 setting Performance for PC2-4200-444
Table 1
Product Type Speed Code Speed Grade max. Clock Frequency @CL5 @CL4 @CL3 min. RAS-CAS-Delay min. Row Precharge Time min. Row Active Time min. Row Cycle Time
-3.7 PC2-4200 4-4-4
Unit -- MHz MHz MHz ns ns ns ns
fCK5 fCK4 fCK3 tRCD tRP tRAS tRC
266 266 200 15 15 45 60
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Data Sheet
5
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Overview
Table 2
High Performance for PC2-3200 -5 PC2-3200 3-3-3 @CL5 @CL4 @CL3 fCK5 fCK4 fCK3 tRCD tRP tRAS tRC 200 200 200 15 15 40 55 Unit -- MHz MHz MHz ns ns ns ns
Product Type Speed Code Speed Grade max. Clock Frequency
min. RAS-CAS-Delay min. Row Precharge Time min. Row Active Time min. Row Cycle Time
1.2
Description
The INFINEON HYS72T[64/128/256]xxxHR-[3.7/5]-B module family are Registered DIMM modules with 30,0 mm height based on DDR2 technology. DIMMs are available as ECC modules in 64M x72 (512 MB), 128M x72 (1 GB), 256M x72 (2GB) organization and density, intended for mounting into 240-Pin connector sockets. The memory array is designed with 512-Mbit Double-Data-Rate-Two (DDR2) Synchronous DRAMs. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. Decoupling capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.
Table 3 PC2-4200
Ordering Information for RoHS Compliant Products Compliance Code2) 512 MB 1Rx8 PC2-4200R-444-12-A0 1 GB 1Rx4 PC2-4200R-444-12-C0 1 GB 2Rx8 PC2-4200R-444-12-B0 2 GB 2Rx4 PC2-4200R-444-12-J1 512 MB 1Rx8 PC2-3200R-333-12-A0 1 GB 1Rx4 PC2-3200R-333-12-C0 1 GB 2Rx8 PC2-3200R-333-12-B0 2 GB 2Rx4 PC2-3200R-333-12-J1 Description 1 Rank ECC 1 Rank ECC 2 Ranks, ECC 2 Ranks, ECC 1 Rank ECC 1 Rank ECC 2 Ranks, ECC 2 Ranks, ECC SDRAM Technology 512 Mbit (x8) 512 Mbit (x4) 512 Mbit (x8) 512 Mbit (x4) 512 Mbit (x8) 512 Mbit (x4) 512 Mbit (x8) 512 Mbit (x4)
Product Type1) HYS72T64000HR-3.7-B HYS72T128000HR-3.7-B HYS72T128020HR-3.7-B HYS72T256220HR-3.7-B PC2-3200 HYS72T64000HR-5-B HYS72T128000HR-5-B HYS72T128020HR-5-B HYS72T256220HR-5-B
1) All part numbers end with a place code, designating the silicon die revision. Example: HYS72T64000HR-3.7-B, indicating Rev. "B" dies are used for DDR2 SDRAM components. For all INFINEON DDR2 module and component nomenclature see Chapter 6 of this data sheet. 2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2-4200R-444- 12-A0", where 4200R means Registered DIMM modules with 4.26 GB/sec Module Bandwidth and "444-12" means Column Address Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2 and produced on the Raw Card "A"
Data Sheet
6
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Overview
Table 4 DIMM Density 512 MB 1 GB 1 GB 2 GB Table 5
Address Format Module Organization 64M x72 128M x72 128M x72 256M x72 Memory Ranks 1 1 2 2 ECC/ Non-ECC ECC ECC ECC ECC # of SDRAMs 9 18 18 36 # of row/bank/column Raw bits Card 14/2/10 14/2/11 14/2/10 14/2/11 F H G J
Components on Modules 1) DRAM Components2) HYB18T512800BF HYB18T512400BF HYB18T512800BF HYB18T512400BF DRAM Density 512 Mbit 512 Mbit 512 Mbit 512 Mbit DRAM Organisation 512M x8 512M x4 512M x8 512M x4
Product Type2) HYS72T64000HR HYS72T128000HR HYS72T128020HR HYS72T256220HR
1) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet. 2) Green Product
Data Sheet
7
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Pin Configuration and Block Diagrams
2
2.1
Pin Configuration and Block Diagrams
Pin Configuration
explained in Table 7 and Table 8 respectively. The pin numbering is depicted in Figure 1.
The pin configuration of the Registered DDR2 SDRAM DIMM is listed by function in Table 6 (240 pins). The abbreviations used in columns Pin and Buffer Type are Table 6 Pin Configuration of RDIMM Name Pin Buffer Type Type I I SSTL SSTL Function
Pin or Ball No. Clock Signals 185 186
CK0 CK0
Clock Signal CK0, Complementary Clock Signal CK0 The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and the falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. Clock Enables 1:0 Activates the DDR2 SDRAM CK signal when HIGH and deactivates the CK signal when LOW. By deactivating the clocks, CKE0 initiates the Power Down Mode or the Self Refresh Mode. Note: 2-Ranks module Not Connected Note: 1-Rank module
52 171
CKE0 CKE1
I I
SSTL SSTL
NC Control Signals 193 76 S0 S1
NC
--
I I
SSTL SSTL
Chip Select Rank 1:0 Enables the associated DDR2 SDRAM command decoder when LOW and disables the command decoder when HIGH. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1. The input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are high. When S is HIGH, all register outputs (except CK, ODT and Chip select) remain in the previous state. Note: 2-Ranks module Not Connected Note: 1-Rank module Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) When sampled at the cross point of the rising edge of CK, and falling edge of CK, RAS, CAS and WE define the operation to be executed by the SDRAM.
NC 192 74 73 RAS CAS WE
NC I I I
-- SSTL SSTL SSTL
Data Sheet
8
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Pin Configuration and Block Diagrams Table 6 Pin Configuration of RDIMM (cont'd) Name Pin Buffer Type Type CMOS Function Register Reset The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When LOW, all register outputs will be driven LOW and the PLL clocks to the DRAMs and the register(s) will be set to low-level. The PLL will remain synchronized with the input clock. Bank Address Bus 1:0 Selects internal SDRAM memory bank Bank Address Bus 2 Greater than 512Mb DDR2 SDRAMS Not Connected Less than 1Gb DDR2 SDRAMS Address Bus 12:0, Address Signal 10/AutoPrecharge During a Bank Activate command cycle, defines the row address when sampled at the crosspoint of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is HIGH, autoprecharge is selected and BA[1:0] defines the bank to be precharged. If AP is LOW, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA[1:0] to control which bank(s) to precharge. If AP is HIGH, all banks will be precharged regardless of the state of BA[1:0] inputs. If AP is LOW, then BA[1:0] are used to define which bank to precharge.
Pin or Ball No. 18
RESET I
Address Signals 71 190 54 BA0 BA1 BA2 NC 188 183 63 182 61 60 180 58 179 177 70 57 176 196 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 A12 A13 NC 174 A14 NC I I I I I I I I I I I I I I I I I I I NC I NC SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL -- SSTL -- Address Signal 13 Note: modules based on x4, x8 Not Connected Note: modules based on x16 Address Signal 14 Note: 2 Gbit based module Not Connected Note: 1 Gbit based module or smaller
Data Sheet
9
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Pin Configuration and Block Diagrams Table 6 Pin Configuration of RDIMM (cont'd) Name Pin Buffer Type Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL 10 Rev. 1.10, 2006-03 05112005-YMIX-KUOQ Function
Pin or Ball No. Data Signals 3 4 9 10 122 123 128 129 12 13 21 22 131 132 140 141 24 25 30 31 143 144 149 150 33 34 39 40 152 153 158 159 80 81 86 87 199 200 205 Data Sheet
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38
Data Bus 63:0 Data Input/Output pins
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Pin Configuration and Block Diagrams Table 6 Pin Configuration of RDIMM (cont'd) Name DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 Pin Buffer Type Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Check Bits 7:0 Check Bit Input / Output pins Note: NC on Non-ECC module Function Data Bus 63:0
Pin or Ball No. 206 89 90 95 96 208 209 214 215 98 99 107 108 217 218 226 227 110 111 116 117 229 230 235 236 Check Bits 42 43 48 49 161 162 167 168
Data Sheet
11
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Pin Configuration and Block Diagrams Table 6 Pin Configuration of RDIMM (cont'd) Name Pin Buffer Type Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL -- SSTL -- SSTL -- SSTL -- SSTL -- Not Connected Note: x8 based DIMMs only NC 135 Not Connected Note: x4 based DIMMs DQS10 I/O NC 147 NC Not Connected Note: x8 based DIMMs only Not Connected Note: x4 based DIMMs DQS11 I/O NC 156 NC Not Connected Note: x8 based DIMMs only Not Connected Note: x4 based DIMMs DQS12 I/O NC 203 NC Not Connected Note: x8 based DIMMs only Not Connected Note: x4 based DIMMs DQS13 I/O NC NC Not Connected Note: x8 based DIMMs only Not Connected Note: x4 based DIMMs Function
Pin or Ball No. Data Strobe Bus 7 6 16 15 28 27 37 36 84 83 93 92 105 104 114 113 46 45 126
DQS0 DQS0 DQS1 DQS1 DQS2 DQS2 DQS3 DQS3 DQS4 DQS4 DQS5 DQS5 DQS6 DQS6 DQS7 DQS7 DQS8 DQS8 DQS9
Data Strobes 17:0 The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode the data strobe is sourced by the DDR2 SDRAM and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS. If the module is to be operated in single ended strobe mode, all DQS signals must be tied on the system board to VSS through a 20 ohm to 10 Kohm resistor and DDR2 SDRAM mode registers programmed appropriately. Note: See block diagram for corresponding DQ signals
Data Sheet
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Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Pin Configuration and Block Diagrams Table 6 Pin Configuration of RDIMM (cont'd) Name Pin Buffer Type Type SSTL -- SSTL -- SSTL -- SSTL -- SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Masks 7:0 The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is LOW but blocks the write operation if it is HIGH. In Read mode, DM lines have no effect. Note: x8 based module Function Not Connected Note: x8 based DIMMs only NC 224 NC Not Connected Note: x4 based DIMMs DQS15 I/O NC 233 NC Not Connected Note: x8 based DIMMs only Not Connected Note: x4 based DIMMs DQS16 I/O NC 165 NC Not Connected Note: x8 based DIMMs only Not Connected Note: x4 based DIMMs DQS17 I/O NC 125 134 146 155 202 211 223 232 164 125 134 146 155 202 211 223 232 164 DQS9 NC I/O Not Connected Note: x8 based DIMMs only Not Connected Note: x4 based DIMMs Data Strobes 17:9 Note: x4 based module DQS10 I/O DQS11 I/O DQS12 I/O DQS13 I/O DQS14 I/O DQS15 I/O DQS16 I/O DQS17 I/O DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 I I I I I I I I I
Pin or Ball No. 212
DQS14 I/O
Data Sheet
13
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Pin Configuration and Block Diagrams Table 6 Pin Configuration of RDIMM (cont'd) Name Pin Buffer Type Type I I/O CMOS OD Function
Pin or Ball No. EEPROM 120 119
SCL SDA
Serial Bus Clock This signal is used to clock data into and out of the SPD EEPROM. Serial Bus Data This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must be connected from SDA to VDDSPD on the motherboard to act as a pull-up. Serial Address Select Bus 2:0 These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range I/O Reference Voltage Reference voltage for the SSTL-18 inputs. EEPROM Power Supply Serial EEPROM positive power supply, wired to a separated power pin at the connector which supports from 1.7 Volt to 3.6 Volt. I/O Driver Power Supply Power and ground for the DDR SDRAM Power Supply Power and ground for the DDR SDRAM Ground Plane Power and ground for the DDR SDRAM
239 240 101 Power Supplies 1 238
SA0 SA1 SA2
I I I AI
CMOS CMOS CMOS --
VREF VDDSPD
PWR --
51, 56, 62, 72, 75, VDDQ 78, 170, 175,, 181, 191, 194 53, 59, 64, 67, 69, VDD 172, 178, 184,, 187, 189, 197 2, 5, 8, 11, 14, 17, VSS 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 65, 66, 79, 82, 85, 88, 91, 94, 97, 100, 103, 106, 109, 112, 115, 118, 121, 124, 127, 130, 133, 136, 139, 142, 145, 148, 151, 154, 157, 160, 163, 166, 169, 198, 201, 204, 207, 210, 213, 216, 219, 222, 225, 228, 231, 234, 237
PWR --
PWR --
GND --
Data Sheet
14
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Pin Configuration and Block Diagrams Table 6 Pin Configuration of RDIMM (cont'd) Name Pin Buffer Type Type NC -- Function
Pin or Ball No. Other Pins 19, 55, 68, 102, 137, 138, 173, 220, 221 195 77
NC
Not connected Pins not connected on Infineon RDIMM's On-Die Termination Control 1:0 Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR2 SDRAM mode register. Note: 2-Ranks module
ODT0 ODT1
I I
SSTL SSTL
NC
NC
-- Note: 1-Rank modules
Table 7 SSTL CMOS OD
Abbreviations for Buffer Type Description Serial Stub Terminated Logic (SSTL_18) CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR. Abbreviations for Pin Type Description Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Usable Not Connected
Abbreviation
Table 8 I O I/O AI PWR GND NU NC
Abbreviation
Data Sheet
15
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Pin Configuration and Block Diagrams
Figure 1
Pin Configuration for RDIMM (240 pins)
Data Sheet
16
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Pin Configuration and Block Diagrams
2.2
Block Diagrams
Figure 2 Notes
Block Diagram Raw Card A RDIMM (x72, 1 Rank, x8) 2. S0 connects to DCS and VDD connects to CSR on the register.
1. Unless otherwise noted, resistors are 22 5 %
Data Sheet
17
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Pin Configuration and Block Diagrams
Figure 3 Notes
Block Diagram Raw Card C RDIMM (x72, 1 Rank, x4) 3. CSR of register1 and DCS of register2 connects to VDD. 4. RESET, PCK7 and PCK7 connect to both registers.
1. Unless otherwise noted, resistors are 22 5 % 2. S0 connects to DCS of register1 and CSR of register2.
Data Sheet
18
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Pin Configuration and Block Diagrams
Figure 4 Notes
Block Diagram Raw Card B RDIMM (x72, 2 Ranks, x8) 2. RS0 and RS1 alternate between the back and front sides of the DIMM.
1. Unless otherwise noted, resistors are 22 5 %
Data Sheet
19
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Pin Configuration and Block Diagrams
Figure 5 Notes
Block Diagram Raw Card J RDIMM (x72, 2Ranks, x4) 3. S0 connects to DCS and S1 Connects to CSR on a pair of registers. S1 connects to DCS and S0 connects to CSR on another pair of registers. 4. RESET, PCK7 and PCK7 connect to all registers.
1. Unless otherwise noted, resistors are 22 5 % 2. RS0 and RS1 alternate between the bottom and surface sides of the DIMM.
Data Sheet
20
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Electrical Characteristics
3
3.1
Electrical Characteristics
Absolute Maximum Ratings
Caution is needed not to exceed abolute maximum ratings of the DRAM device listed in Table 9 at any time. Table 9 Symbol Absolute Maximum Ratings Parameter Voltage on VDD pin relative to VSS Voltage on VDDQ pin relative to VSS Voltage on VDDL pin relative to VSS Voltage on any pin relative to VSS Storage Temperature Rating -1.0 to +2.3 -0.5 to +2.3 -0.5 to +2.3 -0.5 to +2.3 -55 to +100 Unit V V V V C Notes
1)2) 2)3) 2)3) 2) 2)3)
VDD VDDQ VDDL VIN, VOUT TSTG
1) Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV. 3) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Table 10 Symbol
DRAM Component Operating Temperature Range Parameter Operating Temperature Rating 0 to 95 Unit C Notes
1)2)3)
TOPER
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM. 2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case temperature must be maintained between 0 - 95 C under all other specification parameters. 3) Self-Refresh period is hard-coded in the chip and therefore it is imperative that the system ensures the DRAM is below 85 C case temperature before initiating self-refresh operation.
3.2
DC Characteristics
Table 11 Symbol
Recommended DC Operating Conditions (SSTL_18) Parameter Supply Voltage Supply Voltage for DLL Supply Voltage for Output Input Reference Voltage Rating Min. Typ. 1.8 1.8 1.8 0.5 x VDDQ Max. 1.9 1.9 1.9 0.51 x VDDQ V V V V
1) 1) 1) 2)3)
Unit
Notes
VDD VDDDL VDDQ VREF VTT
1) 2) 3) 4)
1.7 1.7 1.7 0.49 x VDDQ
4) Termination Voltage VREF - 0.04 VREF VREF + 0.04 V VDDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. Peak to peak ac noise on VREF may not exceed 2% VREF (dc) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in die dc level of VREF.
Data Sheet
21
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Electrical Characteristics
Table 12
ODT DC Electrical Characteristics Symbol Rtt1(eff) Rtt2(eff) Rtt3(eff) Min. 60 120 40 Nom. 75 150 50 Max. 90 180 60 Unit Notes
1)
Parameter / Condition Termination resistor impedance value for EMRS(1)[A6,A2] = [0,1]; 75 Ohm Termination resistor impedance value for EMRS(1)[A6,A2] =[1,0]; 150 Ohm Termination resistor impedance value for EMRS(1)(A6,A2)=[1,1]; 50 Ohm Deviation of VM with respect to VDDQ / 2
1)
1)
2) delta VM -6.00 -- + 6.00 % 1) Measurement Definition for Rtt(eff): Apply VIH(ac) and VIL(ac) to test pin separately, then measure current I(VIHac) and I(VILac) respectively. Rtt(eff) = (VIH(ac) - VIL(ac)) /(I(VIHac) - I(VILac)). 2) Measurement Definition for VM: Turn ODT on and measure voltage (VM) at test pin (midpoint) with no load: delta VM = ((2 x VM / VDDQ) - 1) x 100%
Table 13 Symbol IIL IOL
Input and Output Leakage Currents Parameter / Condition Input Leakage Current; any input 0 V < VIN < VDD Output Leakage Current; 0 V < VOUT < VDDQ Min. -2 -5 Max. +2 +5 Unit A A Notes
1) 2)
1) All other pins not under test = 0 V 2) DQ's, LDQS, LDQS, UDQS, UDQS, DQS, DQS, RDQS, RDQS are disabled and ODT is turned off
Table 14 Symbol CCK CDCK CI CDI CIO CDIO
Input / Output Capacitance Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS, RDQS, RDQS Input/output capacitance delta, DQ, DM, DQS, DQS, RDQS, RDQS -- -- -- Min. Max. Unit pF pF pF pF pF pF
Data Sheet
22
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Electrical Characteristics
3.3
AC Characteristics
3.3.1
Speed Grade Definitions
All Speed grades faster than DDR2-DDR400B comply with DDR2-DDR400B timing specifications(tCK = 5ns with tRAS = 40ns). List of Speed Grade Definition tables: * * Table 15 "Speed Grade Definition Speed Bins for DDR2-533C" on Page 23 Table 16 "Speed Grade Definition Speed Bins for DDR2-400B" on Page 24 Speed Grade Definition Speed Bins for DDR2-533C DDR2-533C -3.7 4-4-4 Symbol @ CL = 3 @ CL = 4 @ CL = 5 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Min. 5 3.75 3.75 45 60 15 15 Max. 8 8 8 70000 -- -- -- Unit Note
Table 15
Speed Grade IFX Sort Name CAS-RCD-RP latencies Parameter Clock Frequency
tCK
-- ns ns ns ns ns ns ns
1)2)3)4) 1)1)1)1) 1)1)1)1) 1)1)1)1)5) 1)1)1)1) 1)1)1)1) 1)1)1)1)
tCK tCK tCK tRAS tRC tRCD tRP
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only. 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
Data Sheet
23
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Electrical Characteristics
Table 16
Speed Grade Definition Speed Bins for DDR2-400B DDR2-400B -5 3-3-3 Symbol @ CL = 3 @ CL = 4 @ CL = 5 Min. 5 5 5 40 55 15 15 Max. 8 8 8 70000 -- -- -- Unit Note
Speed Grade IFX Sort Name CAS-RCD-RP latencies Parameter Clock Frequency
tCK
-- ns ns ns ns ns ns ns
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4)
Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time
tCK tCK tCK tRAS tRC tRCD tRP
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only. 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
Data Sheet
24
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Electrical Characteristics
3.3.2
* *
AC Timing Parameters
List of AC timing parameter tables. Table 17 "Timing Parameter by Speed Grade - DDR2-533" on Page 25 Table 18 "Timing Parameter by Speed Grade - DDR2-400" on Page 27 Timing Parameter by Speed Grade - DDR2-533 Symbol DDR2-533 Min. DQ output access time from CK / CK CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time Max. ps 2 0.45 3 0.45 WR + tRP -- 0.55 -- 0.55 -- -- -- -- -- -- 300 + 0.25 -- -- -- -- Unit Notes1)2)3)4)
5)6)7)
Table 17 Parameter
tAC tCCD tCH tCKE tCL tDAL
tCK tCK tCK tCK tCK
ns ps ps
Minimum time clocks remain ON after CKE tDELAY asynchronously drops LOW DQ and DM input hold time (differential data strobe) DQ and DM input hold time (single ended data strobe) DQS output access time from CK / CK DQS input low (high) pulse width (write cycle)
tIS + tCK + tIH
225 -25 0.35 0.35 -- - 0.25 100 -25 0.2 0.2 MIN. (tCL, tCH) -- 375 0.6 250
tDH(base) tDH1(base)
DQ and DM input pulse width (each input) tDIPW
tCK
ps
tDQSCK tDQSL,H
tCK
ps
DQS-DQ skew (for DQS & associated DQ tDQSQ signals) Write command to 1st DQS latching transition DQ and DM input setup time (differential data strobe)
tDQSS tDS(base)
tCK
ps ps
DQ and DM input setup time (single ended tDS1(base) data strobe) DQS falling edge hold time from CK (write tDSH cycle) DQS falling edge to CK setup time (write cycle) Clock half period Data-out high-impedance time from CK / CK Address and control input hold time Address and control input pulse width (each input) Address and control input setup time
tCK tCK
tDSS tHP tHZ tIH(base) tIPW tIS(base)
tAC.MAX
-- -- --
ps ps
tCK
ps
Data Sheet
25
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Electrical Characteristics Table 17 Parameter DQ low-impedance time from CK / CK DQS low-impedance from CK / CK Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS Data hold skew factor Average periodic refresh Interval Precharge-All (4 banks) command period Read preamble Read postamble Active bank A to Active bank B command period Internal Read to Precharge command delay Write preamble Timing Parameter by Speed Grade - DDR2-533 (cont'd) Symbol DDR2-533 Min. Max. 2x Unit Notes1)2)3)4)
5)6)7)
tLZ(DQ) tLZ(DQS) tMRD tOIT tQH tQHS tREFI tRP tRPRE tRPST tRRD tRTP
tAC.MIN tAC.MIN
2 0
tAC.MAX tAC.MAX
-- 12 -- 400 7.8 3.9 -- 1.1 0.60 -- -- -- -- 0.60 --
ps ps
tCK
ns ps s s ns
8) 9)
tHP -tQHS
-- -- --
tRP
0.9 0.40 7.5 10 7.5 0.25 x tCK 0.40 15
tCK tCK
ns ns ns
tWPRE Write postamble tWPST Write recovery time for write without Auto- tWR
Precharge Write recovery time for write with AutoPrecharge Internal Write to Read command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to Read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command Exit Self-Refresh to Read command WR
tCK tCK
ns
tWR/tCK
7.5 2 6 - AL 2 -- -- -- -- -- --
tCK
ns
tWTR tXARD tXARDS tXP tXSNR tXSRD
tCK tCK tCK
ns
tRFC +10
200
tCK
1) For details and notes see the relevant INFINEON component data sheet 2) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V. See notes 4)5)6)7) 3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 5) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode. 6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 7) The output timing reference voltage level is VTT. 8) 0 C TCASE 85 C
Data Sheet
26
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Electrical Characteristics
9) 85 C < TCASE 95 C
Table 18 Parameter
Timing Parameter by Speed Grade - DDR2-400 Symbol DDR2-400 Min. Max. ps 2 0.45 3 0.45 WR + tRP -- 0.55 -- 0.55 -- -- -- -- -- -- 350 + 0.25 -- -- -- -- Unit Notes1)2)3)4)
5)6)7)
DQ output access time from CK / CK CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time
tAC tCCD tCH tCKE tCL tDAL
tCK tCK tCK tCK tCK
ns ps ps
Minimum time clocks remain ON after CKE tDELAY asynchronously drops LOW DQ and DM input hold time (differential data strobe) DQ and DM input hold time (single ended data strobe) DQS output access time from CK / CK DQS input low (high) pulse width (write cycle)
tIS + tCK + tIH
275 -25 0.35 0.35 -- - 0.25 150 -25 0.2 0.2 MIN. (tCL, tCH) -- 475 0.6 350 2x
tDH(base) tDH1(base)
DQ and DM input pulse width (each input) tDIPW
tCK
ps
tDQSCK tDQSL,H
tCK
ps
DQS-DQ skew (for DQS & associated DQ tDQSQ signals) Write command to 1st DQS latching transition DQ and DM input setup time (differential data strobe)
tDQSS tDS(base)
tCK
ps ps
DQ and DM input setup time (single ended tDS1(base) data strobe) DQS falling edge hold time from CK (write tDSH cycle) DQS falling edge to CK setup time (write cycle) Clock half period Data-out high-impedance time from CK / CK Address and control input hold time Address and control input pulse width (each input) Address and control input setup time DQ low-impedance time from CK / CK DQS low-impedance from CK / CK Mode register set command cycle time Data Sheet
tCK tCK
tDSS tHP tHZ tIH(base) tIPW tIS(base) tLZ(DQ) tLZ(DQS) tMRD
27
tAC.MAX
-- -- --
ps ps
tCK
ps ps ps
tAC.MIN tAC.MIN
2
tAC.MAX tAC.MAX
--
tCK
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Electrical Characteristics Table 18 Parameter OCD drive mode output delay Data output hold time from DQS Data hold skew factor Average periodic refresh Interval Precharge-All (4 banks) command period Timing Parameter by Speed Grade - DDR2-400 Symbol DDR2-400 Min. Max. 12 -- 450 7.8 3.9 -- 1.1 0.60 -- -- -- -- 0.60 -- ps s s ns
8) 9)
Unit ns
Notes1)2)3)4)
5)6)7)
tOIT tQH tQHS tREFI
0
tHP -tQHS
-- -- --
tRP Read preamble tRPRE Read postamble tRPST Active bank A to Active bank B command tRRD
period Internal Read to Precharge command delay Write preamble
tRP
0.9 0.40 7.5 10 7.5 0.25 x tCK 0.40 15
tCK tCK
ns ns ns
tRTP
tWPRE Write postamble tWPST Write recovery time for write without Auto- tWR
Precharge WR
tCK tCK
ns
Write recovery time for write with AutoPrecharge Internal Write to Read command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to Read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command Exit Self-Refresh to Read command
tWR/tCK
10 2 6 - AL 2 -- -- -- -- -- --
tCK
ns
tWTR tXARD tXARDS tXP tXSNR tXSRD
tCK tCK tCK
ns
tRFC +10
200
tCK
1) For details and notes see the relevant INFINEON component data sheet 2) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V. See notes 4)5)6)7) 3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 5) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode. 6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 7) The output timing reference voltage level is VTT. 8) 0 C TCASE 85 C 9) 85 C < TCASE 95 C
Data Sheet
28
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Electrical Characteristics
3.3.3
ODT AC Electrical Characteristics
Table 19 Symbol
ODT AC Characteristics and Operating Conditions for DDR2-533 and DDR2-400 Parameter / Condition ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Modes) ODT turn-off delay ODT turn-off Values Min. Max. 2 2 Unit Note
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
tCK
ns ns
1)
tAC.MIN tAC.MAX + 1 ns tAC.MIN + 2 ns 2 tCK + tAC.MAX + 1 ns
2.5 2.5
tCK
2)
tAC.MIN tAC.MAX + 0.6 ns ns ODT turn-off (Power-Down Modes) tAC.MIN + 2 ns 2.5 tCK + tAC.MAX + 1 ns ns ODT to Power Down Mode Entry Latency 3 -- tCK ODT Power Down Exit Latency 8 -- tCK
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measure from tAOND. 2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
Data Sheet
29
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Electrical Characteristics
3.4
* * *
IDD Specifications and Conditions
List of tables defining IDD Specifications and Conditions. Table 20 "IDD Measurement Conditions" on Page 30 Table 22 "IDD Specification for HYS72T[64/128/256]xxxHR-3.7-B" on Page 32 Table 23 "IDD Specification for HYS72T[64/128/256]xxxHR-5-B" on Page 33
Table 20 Parameter
IDD Measurement Conditions 1)2)3)4)5)6)
Symbol
Operating Current 0 One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
IDD0
Operating Current 1 IDD1 One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, tRCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Precharge Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Precharge Power-Down Current Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2N
IDD2P
Precharge Quiet Standby Current IDD2Q All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE, Data bus inputs are FLOATING. Active Standby Current IDD3N Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA. Active Power-Down Current IDD3P(0) All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit); Active Power-Down Current IDD3P(1) All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit); Operating Current IDD4W urst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; Burst Refresh Current IDD5B tCK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Distributed Refresh Current IDD5D tCK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Data Sheet
30
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Electrical Characteristics Table 20 Parameter
IDD Measurement Conditions (cont'd)1)2)3)4)5)6)
Symbol
Self-Refresh Current IDD6 CKE 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 C max. All Bank Interleave Read Current IDD7 All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address bus inputs are STABLE during DESELECTS. Iout = 0 mA. 1) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V 2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled. 3) Definitions for IDD see Table 21 4) IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module
level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH. 5) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P 6) For details and notes see the relevant INFINEON component data sheet
Table 21 Parameter LOW STABLE FLOATING
Definitions for IDD Description
VIN VIL(ac).MAX, HIGH is defined as VIN VIH(ac).MIN
inputs are stable at a HIGH or LOW level inputs are VREF = VDDQ /2 inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ signals not including mask or strobes
SWITCHING
Data Sheet
31
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Electrical Characteristics
Table 22
IDD Specification for HYS72T[64/128/256]xxxHR-3.7-B
HYS72T128000HR-3.7-B HYS72T128020HR-3.7-B HYS72T256220HR-3.7-B HYS72T64000HR-3.7-B Unit Note1)
Product Type
Organization
512 MB 1 Rank x72 -3.7
1 GB 1 Rank x72 -3.7 Max. 1670 1850 630 1180 1130 1000 660 1270 2480 2480 2840 660 126 3110
1 GB 2 Ranks x72 -3.7 Max. 980 1070 460 1010 960 830 490 1100 1380 1380 1560 490 126 1700
2 GB 2 Ranks x72 -3.7 Max. 1800 1980 750 1870 1760 1510 820 2050 2610 2610 2970 820 252 3240 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
2) 2) 3) 3) 3) 3) 3) 3) 2) 2) 2) 3)4) 3)4) 2)
Symbol
Max. 920 1010 390 670 650 580 410 720 1320 1320 1500 410 63 1640
IDD0 IDD1 IDD2P IDD2N IDD2Q IDD3P( MRS = 0) IDD3P( MRS = 1) IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
1) Module IDDis calculated on the basis of component IDDand includes currents of Registers and PLL. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled. 2) The other rank is in IDD2P Precharge Power-Down Current mode 3) Both ranks are in the same IDDcurrent mode 4) IDD5D and IDD6 values are for 0 C TCase 85 C
Data Sheet
32
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Electrical Characteristics
Table 23
IDD Specification for HYS72T[64/128/256]xxxHR-5-B
HYS72T128000HR-5-B HYS72T128020HR-5-B HYS72T256220HR-5-B HYS72T64000HR-5-B Unit Note1)
Product Type
Organization
512 MB 1 Rank x72 -5
1 GB 1 Rank x72 -5 Max. 1500 1670 530 1020 980 840 570 1110 2120 2120 2660 570 126 2940
1GB 2 Ranks x72 -5 Max. 890 970 400 890 850 710 440 980 1190 1190 1460 440 126 1610
2 GB 2 Ranks x72 -5 Max. 1630 1790 660 1630 1560 1270 730 1810 2240 2240 2780 730 252 3070 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
2) 2) 3) 3) 3) 3) 3) 3) 2) 2) 2) 3)4) 3)4) 2)
Symbol
Max. 820 910 340 580 560 490 360 630 1130 1130 1400 360 63 1540
IDD0 IDD1 IDD2P IDD2N IDD2Q IDD3P( MRS = 0) IDD3P( MRS = 1) IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
1) Module IDD is calculated on the basis of component IDDand includes currents of Registers and PLL. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled. 2) The other rank is in IDD2P Precharge Power-Down Current mode 3) Both ranks are in the same IDDcurrent mode 4) IDD5D and IDD6 values are for 0 C TCase 85 C.
Data Sheet
33
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Electrical Characteristics
3.4.1
* *
IDD Test Conditions
For testing the IDD parameters, the timing parameters as shown in the tables below are used. Table 24 "IDD Measurement Test Condition for DDR2-533C" on Page 34 Table 25 "IDD Measurement Test Condition for DDR2-400B" on Page 34
Table 24 Parameter
IDD Measurement Test Condition for DDR2-533C
Symbol CLIDD tCK.IDD tRCD.IDD tRC.IDD tRRD.IDD tRAS.MIN.IDD tRAS.MAX.IDD tRP.IDD tRFC.IDD tREFI tREFI 7.8 3.9 0C TCASE 85C 85C TCASE 95C -3.7 DDR2-533C 3 3.75 15 60 7.5 10 45 7000 15 Unit Notes tCK ns ns ns ns ns ns ns ns ns s s
1) 2)
CAS Latency Clock Cycle Time Active to Read or Write delay Active to Active / Auto-Refresh command period Active bank A to Active bank B command delay Active to Precharge Command Precharge Command Period Auto-Refresh to Active / Auto-Refresh command period Average periodic Refresh interval
1) x4 & x8 (1 kB page size) 2) x16 (2 kB page size)
Table 25 Parameter
IDD Measurement Test Condition for DDR2-400B
Symbol CLIDD tCK.IDD tRCD.IDD tRC.IDD tRRD.IDD tRAS.MIN.IDD tRAS.MAX.IDD tRP.IDD tRFC.IDD tREFI tREFI 7.8 3.9 0C TCASE 85C 85C TCASE 95C -5 DDR2-400B 3 5 15 55 7.5 10 40 7000 15 Unit Notes tCK ns ns ns ns ns ns ns ns ns s s
1) 2)
CAS Latency Clock Cycle Time Active to Read or Write delay Active to Active / Auto-Refresh command period Active bank A to Active bank B command delay Active to Precharge Command Precharge Command Period Auto-Refresh to Active / Auto-Refresh command period Average periodic Refresh interval
1) x4 & x8 (1 kB page size) 2) x16 (2 kB page size)
Data Sheet
34
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Electrical Characteristics
3.4.2
On Die Termination (ODT) Current
current consumption for any terminated input pin, depends on the input pin is in tri-state or driving 0 or 1, as long a ODT is enabled during a given period of time.
The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1). Depending on address bits A[6,2] in the EMRS(1) a "weak" or "strong" termination can be selected. The Table 26 Parameter Enabled ODT current per DQ ODT is HIGH; Data Bus inputs are FLOATING ODT current per terminated pin
Symbol Min.
Typ. 6 3 12 6
Max. Unit 7.5 3.75 15 7.5
EMRS(1) State
IODTO
5 2.5 10 5
mA/DQ A6 = 0, A2 = 1 mA/DQ A6 = 1, A2 = 0 mA/DQ A6 = 0, A2 = 1 mA/DQ A6 = 1, A2 = 0
Active ODT current per DQ IODTT ODT is HIGH; worst case of Data Bus inputs are STABLE or SWITCHING.
Note: For power consumption calculations the ODT duty cycle has to be taken into account
Data Sheet
35
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
SPD Codes
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands for serial presence detect. All values with XX in the table are module specific bytes which are defined during production. List of SPD Code Tables * * Table 27 "HYS72T[64/128/256]xxxHR-3.7-B" on Page 36 Table 28 "HYS72T[64/128/256]xxxHR-5-B" on Page 41 HYS72T[64/128/256]xxxHR-3.7-B HYS72T128000HR-3.7-B HYS72T128020HR-3.7-B HYS72T256220HR-3.7-B 2 GByte x72 2 Ranks (x4) Rev. 1.2 HEX 80 08 08 0E 0B 61 48 00 05 3D 50 02 82 04 04 00 0C 04 Rev. 1.10, 2006-03 05112005-YMIX-KUOQ HYS72T64000HR-3.7-B 512MB x72
Table 27
Product Type
Organization
1 GByte x72
1 GByte x72
1 Rank (x8) 1 Rank (x4) 2 Ranks (x8) Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level
PC2- PC2- PC2- PC2- 4200R-444 4200R-444 4200R-444 4200R-444 Rev. 1.2 HEX 80 08 08 0E 0A 60 48 00 05 3D 50 02 82 08 08 00 0C 04 36 Rev. 1.2 HEX 80 08 08 0E 0B 60 48 00 05 3D 50 02 82 04 04 00 0C 04 Rev. 1.2 HEX 80 08 08 0E 0A 61 48 00 05 3D 50 02 82 08 08 00 0C 04
tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device
Data Sheet
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
SPD Codes Table 27 HYS72T[64/128/256]xxxHR-3.7-B (cont'd) HYS72T128000HR-3.7-B HYS72T128020HR-3.7-B HYS72T256220HR-3.7-B 2 GByte x72 2 Ranks (x4) Rev. 1.2 HEX 38 01 01 07 07 3D 50 50 60 3C 1E 3C 2D 01 25 37 10 22 3C 1E 1E 00 00 3C 69 80 Rev. 1.10, 2006-03 05112005-YMIX-KUOQ HYS72T64000HR-3.7-B 512MB x72
Product Type
Organization
1 GByte x72
1 GByte x72
1 Rank (x8) 1 Rank (x4) 2 Ranks (x8) Label Code JEDEC SPD Revision Byte# 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Description Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes
PC2- PC2- PC2- PC2- 4200R-444 4200R-444 4200R-444 4200R-444 Rev. 1.2 HEX 38 01 01 04 07 3D 50 50 60 3C 1E 3C 2D 80 25 37 10 22 3C 1E 1E 00 00 3C 69 80 Rev. 1.2 HEX 38 01 01 05 07 3D 50 50 60 3C 1E 3C 2D 01 25 37 10 22 3C 1E 1E 00 00 3C 69 80 Rev. 1.2 HEX 38 01 01 05 07 3D 50 50 60 3C 1E 3C 2D 80 25 37 10 22 3C 1E 1E 00 00 3C 69 80
tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns]
37
Data Sheet
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
SPD Codes Table 27 HYS72T[64/128/256]xxxHR-3.7-B (cont'd) HYS72T128000HR-3.7-B HYS72T128020HR-3.7-B HYS72T256220HR-3.7-B 2 GByte x72 2 Ranks (x4) Rev. 1.2 HEX 1E 28 0F 50 7A 43 29 36 21 41 2A 40 1E 22 C4 8C 61 78 12 FC C1 00 00 00 00 00 Rev. 1.10, 2006-03 05112005-YMIX-KUOQ HYS72T64000HR-3.7-B 512MB x72
Product Type
Organization
1 GByte x72
1 GByte x72
1 Rank (x8) 1 Rank (x4) 2 Ranks (x8) Label Code JEDEC SPD Revision Byte# 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 Description
PC2- PC2- PC2- PC2- 4200R-444 4200R-444 4200R-444 4200R-444 Rev. 1.2 HEX 1E 28 0F 50 7A 43 29 36 21 41 2A 40 1E 22 C4 8C 61 78 12 7E C1 00 00 00 00 00 Rev. 1.2 HEX 1E 28 0F 50 7A 43 29 36 21 41 2A 40 1E 22 C4 8C 61 78 12 F9 C1 00 00 00 00 00 Rev. 1.2 HEX 1E 28 0F 50 7A 43 29 36 21 41 2A 40 1E 22 C4 8C 61 78 12 80 C1 00 00 00 00 00
tDQSQ.MAX [ns] tQHS.MAX [ns]
PLL Relock Time
TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2) JEDEC ID Code of Infineon (3) JEDEC ID Code of Infineon (4) JEDEC ID Code of Infineon (5) JEDEC ID Code of Infineon (6)
Data Sheet
38
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
SPD Codes Table 27 HYS72T[64/128/256]xxxHR-3.7-B (cont'd) HYS72T128000HR-3.7-B HYS72T128020HR-3.7-B HYS72T256220HR-3.7-B 2 GByte x72 2 Ranks (x4) Rev. 1.2 HEX 00 00 xx 37 32 54 32 35 36 32 32 30 48 52 33 2E 37 42 20 20 20 0x xx xx xx Rev. 1.10, 2006-03 05112005-YMIX-KUOQ HYS72T64000HR-3.7-B 512MB x72
Product Type
Organization
1 GByte x72
1 GByte x72
1 Rank (x8) 1 Rank (x4) 2 Ranks (x8) Label Code JEDEC SPD Revision Byte# 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 Description JEDEC ID Code of Infineon (7) JEDEC ID Code of Infineon (8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week
PC2- PC2- PC2- PC2- 4200R-444 4200R-444 4200R-444 4200R-444 Rev. 1.2 HEX 00 00 xx 37 32 54 36 34 30 30 30 48 52 33 2E 37 42 20 20 20 20 2x xx xx xx Rev. 1.2 HEX 00 00 xx 37 32 54 31 32 38 30 30 30 48 52 33 2E 37 42 20 20 20 2x xx xx xx Rev. 1.2 HEX 00 00 xx 37 32 54 31 32 38 30 32 30 48 52 33 2E 37 42 20 20 20 2x xx xx xx
Data Sheet
39
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
SPD Codes Table 27 HYS72T[64/128/256]xxxHR-3.7-B (cont'd) HYS72T128000HR-3.7-B HYS72T128020HR-3.7-B HYS72T256220HR-3.7-B 2 GByte x72 2 Ranks (x4) Rev. 1.2 HEX xx 00 Rev. 1.10, 2006-03 05112005-YMIX-KUOQ HYS72T64000HR-3.7-B 512MB x72
Product Type
Organization
1 GByte x72
1 GByte x72
1 Rank (x8) 1 Rank (x4) 2 Ranks (x8) Label Code JEDEC SPD Revision Byte# 95 - 98 Description Module Serial Number
PC2- PC2- PC2- PC2- 4200R-444 4200R-444 4200R-444 4200R-444 Rev. 1.2 HEX xx 00 Rev. 1.2 HEX xx 00 Rev. 1.2 HEX xx 00
99 - 127 Not used
Data Sheet
40
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
SPD Codes
Table 28
HYS72T[64/128/256]xxxHR-5-B HYS72T128000HR-5-B HYS72T128020HR-5-B HYS72T256220HR-5-B 2 GByte x72 2 Ranks (x4) Rev. 1.2 HEX 80 08 08 0E 0B 61 48 00 05 50 60 02 82 04 04 00 0C 04 38 01 01 07 07 50 60 50 Rev. 1.10, 2006-03 05112005-YMIX-KUOQ HYS72T64000HR-5-B 512MB x72
Product Type
Organization
1 GByte x72
1 GByte x72
1 Rank (x8) 1 Rank (x4) 2 Ranks (x8) Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level
PC2- PC2- PC2- PC2- 3200R-333 3200R-333 3200R-333 3200R-333 Rev. 1.2 HEX 80 08 08 0E 0A 60 48 00 05 50 60 02 82 08 08 00 0C 04 38 01 01 04 07 50 60 50 41 Rev. 1.2 HEX 80 08 08 0E 0B 60 48 00 05 50 60 02 82 04 04 00 0C 04 38 01 01 05 07 50 60 50 Rev. 1.2 HEX 80 08 08 0E 0A 61 48 00 05 50 60 02 82 08 08 00 0C 04 38 01 01 05 07 50 60 50
tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes
tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns]
Data Sheet
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
SPD Codes Table 28 HYS72T[64/128/256]xxxHR-5-B (cont'd) HYS72T128000HR-5-B HYS72T128020HR-5-B HYS72T256220HR-5-B 2 GByte x72 2 Ranks (x4) Rev. 1.2 HEX 60 3C 1E 3C 28 01 35 47 15 27 3C 28 1E 00 00 37 69 80 23 2D 0F 50 7A 3B 25 36 1E Rev. 1.10, 2006-03 05112005-YMIX-KUOQ HYS72T64000HR-5-B 512MB x72
Product Type
Organization
1 GByte x72
1 GByte x72
1 Rank (x8) 1 Rank (x4) 2 Ranks (x8) Label Code JEDEC SPD Revision Byte# 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Description
PC2- PC2- PC2- PC2- 3200R-333 3200R-333 3200R-333 3200R-333 Rev. 1.2 HEX 60 3C 1E 3C 28 80 35 47 15 27 3C 28 1E 00 00 37 69 80 23 2D 0F 50 7A 3B 25 36 1E 42 Rev. 1.2 HEX 60 3C 1E 3C 28 01 35 47 15 27 3C 28 1E 00 00 37 69 80 23 2D 0F 50 7A 3B 25 36 1E Rev. 1.2 HEX 60 3C 1E 3C 28 80 35 47 15 27 3C 28 1E 00 00 37 69 80 23 2D 0F 50 7A 3B 25 36 1E
tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
PLL Relock Time
TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N)
Data Sheet
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
SPD Codes Table 28 HYS72T[64/128/256]xxxHR-5-B (cont'd) HYS72T128000HR-5-B HYS72T128020HR-5-B HYS72T256220HR-5-B 2 GByte x72 2 Ranks (x4) Rev. 1.2 HEX 38 2A 38 1D 21 C4 8C 59 5C 12 30 C1 00 00 00 00 00 00 00 xx 37 32 54 32 35 36 32 Rev. 1.10, 2006-03 05112005-YMIX-KUOQ HYS72T64000HR-5-B 512MB x72
Product Type
Organization
1 GByte x72
1 GByte x72
1 Rank (x8) 1 Rank (x4) 2 Ranks (x8) Label Code JEDEC SPD Revision Byte# 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 Description T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2) JEDEC ID Code of Infineon (3) JEDEC ID Code of Infineon (4) JEDEC ID Code of Infineon (5) JEDEC ID Code of Infineon (6) JEDEC ID Code of Infineon (7) JEDEC ID Code of Infineon (8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 43
PC2- PC2- PC2- PC2- 3200R-333 3200R-333 3200R-333 3200R-333 Rev. 1.2 HEX 38 2A 38 1D 21 C4 8C 59 5C 12 B2 C1 00 00 00 00 00 00 00 xx 37 32 54 36 34 30 30 Rev. 1.2 HEX 38 2A 38 1D 21 C4 8C 59 5C 12 2D C1 00 00 00 00 00 00 00 xx 37 32 54 31 32 38 30 Rev. 1.2 HEX 38 2A 38 1D 21 C4 8C 59 5C 12 B4 C1 00 00 00 00 00 00 00 xx 37 32 54 31 32 38 30
Data Sheet
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
SPD Codes Table 28 HYS72T[64/128/256]xxxHR-5-B (cont'd) HYS72T128000HR-5-B HYS72T128020HR-5-B HYS72T256220HR-5-B 2 GByte x72 2 Ranks (x4) Rev. 1.2 HEX 32 30 48 52 35 42 20 20 20 20 20 0x xx xx xx xx 00 Rev. 1.10, 2006-03 05112005-YMIX-KUOQ HYS72T64000HR-5-B 512MB x72
Product Type
Organization
1 GByte x72
1 GByte x72
1 Rank (x8) 1 Rank (x4) 2 Ranks (x8) Label Code JEDEC SPD Revision Byte# 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 Description Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC2- PC2- PC2- PC2- 3200R-333 3200R-333 3200R-333 3200R-333 Rev. 1.2 HEX 30 48 52 35 42 20 20 20 20 20 20 2x xx xx xx xx 00 Rev. 1.2 HEX 30 30 48 52 35 42 20 20 20 20 20 2x xx xx xx xx 00 Rev. 1.2 HEX 32 30 48 52 35 42 20 20 20 20 20 2x xx xx xx xx 00
99 - 127 Not used
Data Sheet
44
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Package Outlines
5
Package Outlines
0.1 A B C
133.35 128.95 2.7 MAX.
4
4x
1
4 2.5 5 63 55
120 C 0.4
30
1.27 0.1
1.5 0.1
3.8
121
240
2.3 0.1 10
A
(3)
Detail of contacts
0.2
1
0.8 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
Figure 6
Package Outline Raw Card A L-DIM-240-11
Data Sheet
45
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
17.8
B
GLD09655
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Package Outlines
0.1 A B C
133.35 128.95 4 MAX.
4
4x
1
4 2.5 5 63 55
120 C 0.4
30
1.27 0.1
1.5 0.1
3.8
121
240
2.3 0.1 10
A
(3)
Detail of contacts
0.2
1
0.8 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
Figure 7
Package Outline Raw Card C L-DIM-240-13
Data Sheet
46
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
17.8
B
GLD09657
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Package Outlines
0.1 A B C
133.35 128.95 4 MAX.
4
4x
1
4 2.5 5 63 55
120 C 0.4
30
1.27 0.1
1.5 0.1
3.8
121
240
2.3 0.1 10
A
(3)
Detail of contacts
0.2
1
0.8 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
Figure 8
Package Outline Raw Card B L-DIM-240-12
Data Sheet
47
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
17.8
B
GLD09656
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Package Outlines
0.1 A B C
133.35 128.95 4 MAX.
4
4x
1
4 2.5 5 63 55
120 C 0.4
30
1.27 0.1
1.5 0.1
3.8
121
240
2.3 0.1 10
A
3 MIN.
Detail of contacts
0.2
1
0.8 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
Figure 9
Package Outline Raw Card J L-DIM-240-20
Data Sheet
48
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
17.8
B
GLD09659
HYS72T[64/128/256]xxxHR-[3.7/5]-B 240-Pin Registered DDR2 SDRAM
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
6
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
description together with possible values and coding explanation is listed for modules in Table 30 and for components in Table 31.
Infineon's nomenclature uses simple coding combined with some propriatory coding. Table 29 provides examples for module and component product type number as well as the field number. The detailed field Table 29 Nomenclature Fields and Examples Field Number 1 Micro-DIMM DDR2 DRAM Table 30 1 2 3 4 HYS HYB 2 64 18 3 T T 4 64 512 5 0 16
Example for
6 2
7 0 0
8 K A
9 M C
10 -5 -5
11 -A
DDR2 DIMM Nomenclature Values Coding HYS 64 72 T 32 64 128 256 512 Constant Non-ECC ECC DDR2 256 MByte 512 MByte 1 GByte 2 GByte 4 GByte Look up table 1, 2, 4
Field Description INFINEON Modul Prefix Module Data Width [bit] DRAM Technology Memory Density per I/O [Mbit]; Module Density1)
1) Multiplying "Memory Density per I/O" with "Module Data Width" and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes as listed in column "Coding".
Table 31 1 2 3 4
DDR2 DRAM Nomenclature Values Coding Constant SSTL1.8 DDR2 256 Mbit 512 Mbit 1 Gbit 2 Gbit x4 x8 x16 Look up table First Second FBGA, lead-containing FBGA, lead-free DDR2-800E 6-6-6 DDR2-667C 4-4-4 DDR2-667D 5-5-5 DDR2-533C 4-4-4 DDR2-533C CL3 DDR2-400B 3-3-3
Field Description
INFINEON HYB Component Prefix Interface Voltage [V] DRAM Technology Component Density [Mbit] 18 T 256 512 1G 2G
5 6 7 8 9
Raw Card Generation
0 .. 9
Number of Module 0, 2, 4 Ranks Product Variations 0 .. 9 Package, Lead-Free Status Module Type A .. Z D M R U -2.5
5+6 Look up table Look up table 7 SO-DIMM Micro-DIMM Registered Unbuffered PC2-6400 6-6-6 PC2-5300 4-4-4 PC2-5300 5-5-5 PC2-4200 4-4-4 PC2-4200 CL3 PC2-3200 3-3-3 First Second 49 10 9 8
Number of I/Os
40 80 16
Product Variations 0 .. 9 Die Revision Package, Lead-Free Status Speed Grade A B C F -2.5 -3 -3S -3.7 -3.7F -5
10
Speed Grade
-3 -3S -3.7 -3.7F -5
11
Die Revision
-A -B
Data Sheet
Rev. 1.10, 2006-03 05112005-YMIX-KUOQ
www.infineon.com
Published by Infineon Technologies AG

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